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Showing posts with label computer trivia. Show all posts
Showing posts with label computer trivia. Show all posts

Computer bug!!


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Moore's law

Moore's law
Source: Wikipedia
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Computing capability of today's laptops

A small laptop computer today has more computing capability than the equipment used to send a man to moon a few years ago.
Today, computers have made tremendous progress in terms of computing capability. The capability of the simplest laptop today is more than the whole system that was used to send a man to moon in 1970's. In fact, it is many many times more than that.
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Simula

C++ Fact
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ENIAC - the first computer

ENIAC – the first computer – was 80 feet long, 8.5 feet high and several feet wide. It incorporated 18,000 vacuum tubes.

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Popular Posts

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using 2:1 mux 3-input OR gate using 2:1 mux 4-bit carry look ahead adder 4-input mux 4:1 mux 4:1 mux from NAND gates 4x1 mux 8-input mux 8:1 mux 8x1 mux AND gate AND gate using mux AND gate with multiplexer Anirudhan Array and linked list comparison Binary multiplier in digital circuits Binary to thermometer code Binary to thermometer code converter Binary to thermometer decoder Bubble error Bubble error correction C++ Integer to string conversion C++ master C++ string to integer conversion C++ trivia CEDT Flip flop written test Carry bypass adder Carry look ahead adder advantages Carry look ahead adder truth table Cell delay VLSI Clock buffer Clock clipping Clock divider VHDL Clock divider VHDL code Clock gate Clock gate cell Clock gating check example Clock gating for power saving Clock gating in VLSI Clock gating latch Clock gating must read Clock gating timing check Clock insertion Delay Clock multiplexer Clock multiplier Conductivity vs temperature Configurable clock divider VHDL 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violation Hold time violations Hold violation How drive strength impacts delay How to avoid setup and hold time violations How to solve setup and hold violations IC latchup ICG cell ICG clock gating IISCBangalore CEDT AIR IIT BOMBAY RA AIR 295 IIT BOMBAY TA RA AIR IIT Madras IITKharagpur INFOSYS TRAINING MYSORE GENERIC STREAM Implementatin of XNOR gate using NAND gates Implementation Improving the duty cycle of clock Insertion delay Integrated clock gating Jitter K-map LBIST Latch applications Latch phenomenon Latch setup and hold Latch setup time Latch up CMOS Latch up VLSI Latch up condition Latch up current Latch up definition Latch up effect Latch up in MOSFET Latch using 2-input mux Latch using 2x1 mux Latch using multiplexer Latch using mux Latchup prevention Logic race condition Long term jitter MBIST basics MBIST test MOS transistor operation MOSFET MOSFET depletion mode MOSFET operating regions MS DIRECT PHD MTBF Make header dependencies Makefile header dependencies Makefile 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VDTT IEC VLSI VDTT JTM CMOS VHDL clock divider VHDL code for binary to thermometer converter VHDL code for divider VHDL code for frequency divider VHDL interview questions VLSI interview questions for freshers Virtual clock Virtual clock SDC Virtual clock STA Virtual clock VLSI Virtual clock example What is VLSI What is clock gating What is latchup What is metastability What is synchronizer What is transmission gate Why is signleton an anti pattern XNOR gate implementation XNOR gate using mux XNOR using NAND XNOR using NAND gates XNOR using mux XOR gate XOR gate applications XOR gate using NAND XOR gate with NAND gates XOR using NAND XOR using NAND gates XOR using mux Zero cycle hold check Zero cycle timing path Zero hold time Zero setup time Zerocycle paths admissions alert iit mtech types ra ta phd direct phd analog design array carry look ahead adder cell arc cell delay cell delay variation circuit to multiply 2-bit numbers clk divider vhdl clock at complex gate clock domain clock latency clock muxing common body common substrate computer technology JTM VDTT JVL IEC control point counter cut-off cypress semiconductors data check data hold check data invalid window data setup check data structure data to data checks data valid window delay variationn depletion design for testability does jitter impact hold does jitter impact setup fabrication false path example false paths flash ADC flip-flop synchronizer flop-based synchronizer frequency dependant hold function overloading generated clock generic stream infosys training mysore pressure pleasure glitch free clock gating half cycle paths high frequency designs implement function using mux integrated clock gating cell kanpur iit latch timing latch up latchup latchup in MOSFET launch clock leading edge linear operation of MOS linear region linked list lockup register logic families logic gates master clock mbist metastability method signature minimum pulse width minimum pulse width check multi cycle multi cycle path setup hold multi-cycle multi-cycle path multicycle path example multiplier mux-based synchronizer negative level latch network latency newiit iit hyderabad ta ra nmos noise margin non-default hold non-unate observe points overloading parasitics pmos positive level latch receiver recovery and removal checks reset assertion reset deassertion routing rtl design saturation scan chains scan flop semiconductor conductivity sequential design series currentsources set clock gating check set clock latency set false path set false path example set multicycle path set_clock_latency set_data_check set_false_path set_min_pulse_width set_multicycle_path setup checks and hold checks setup hold check signoff skew spare cells synchronizer synchronizer circuit synchronous reset tcl temperature inversion texas qualcomm cadence interview throughput timing arcs timing sense transmission gates transmitter types of clock gating checks unate unateness vector voltage why hold check is on same edge why setup check is on next edge wire width world worst slew propation x-propagation xnor gate using 2x1 mux xor gate using 2x1 mux

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